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| Ordering number :EN5452 Monolithic Digital IC LB1955 Three-Phase Brushless Motor Driver Functions * The LB1955 is a 3-phase brushless motor driver IC that is optimal for applications such as driving the drum motor in VCRs. Features * * * * * Current linear drive FG and PG free Single-voltage power supply Built-in AGC circuit Built-in thermal shutdown circuit Package Dimensions unit: mm 3222-HSOP28 [LB1955] Allowable power dissipation, Pd max - W Ambient temperature, Ta - C SANYO: HSOP28 Specifications Absolute Maximum Ratings at Ta = 25C Parameter Maximum supply voltage Maximum output current Allowable power dissipation Operating temperature Storage temperature Symbol VCCmax IOUT Pdmax Topr Tstg Independent device Conditions Ratings 14.5 1.0 0.60 -20 to +75 -55 to +150 Unit V A W C C Allowable Operating Ranges at Ta = 25C Parameter Supply voltage Hall input amplitude VC input voltage Symbol VCC Vhall VC At the input Conditions Ratings 10.2 to 13.8 70 to 500 0 to 5 Unit V mVp-p V SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 73097HA (OT) No. 5452-1/7 LB1955 Electrical Characteristics at Ta = 25C, VCC = 12 V Parameter [Power Supply] Current drain IC internal power supply [Output] Output saturation voltage VO(sat)1 VO(sat)2 Ior IO = 400 mA VC = 5 V, Rf = 0 IO = 800 mA VC = 5 V, Rf = 0 IO = 100 mA, Rf = 0.47 Sink side Source side Sink side Source side -5 0.4 1.5 0.7 2.0 +5 V V V V % ICC VREF VC = 0 V, LCTR = 6 V 7.0 4.75 10.0 5.0 13.0 5.25 mA V Symbol Conditions Ratings min typ max Unit Output saturation voltage 2 3-phase output current ripple [Hall Amplifier] Input offset voltage Input bias current Common-mode input voltage range [Control] VC pin input bias current Control start voltage VHoff IHb VHCM IVCb VTHVC GMVC VC = 0 V Rf = 0.47 , IO 10 mA With the Hall input logic fixed Rf = 0.47 , IO = 200 mA With the Hall input logic fixed and VG shorted to RF VAGC = 1.4 V UIN VIN, WIN -20 +20 10 5 mV A A V 2.2 5.0 -10 2.25 -1.3 2.5 2.75 A V Open-loop control gain [PG] PG Hall amplifier input offset voltage Peak hold charge current PG comparator threshold PG output high-level voltage PG leakage current [FG] Back emf Schmitt input hysteresis width Ringing canceller Schmitt input hysteresis width FG output high-level voltage FG leakage current [TSD] Thermal shutdown operating temperature Thermal shutdown temperature hysteresis width 0.72 0.9 1.08 A/V VPGoff ISHCHG THPG VPGH ILEAKPG Design target (U, V, W) = (L, L, H) Design target* -10 30 117 4.5 -10 0 +10 mV A % 5.2 +10 V A VSCHG In the back emf Schmitt input increasing direction, Design target In the back emf Schmitt input decreasing direction, Design target 100 0 180 -20 4.5 -10 0 0 +20 5.2 +10 mV mV mV mV V A VSCHR VFGH ILEAKFG In the Schmitt input increasing direction, Design target In the Schmitt input decreasing direction, Design target FGR = 0 V TTSD TSD Design target 180 C Design target 15 C Note: * is provided for when X is the peak value at the 60 position of the lower side of the UIN1 Hall amplifier input: THPG = 1.17X. No. 5452-2/7 LB1955 Pin Assignment WIN2 WIN1 UIN2 U H H H L L L UIN1 Hall input logic V H L L L H H W L L H H H L VIN2 VIN1 Truth table Source sink 1 2 3 4 5 6 W phase V phase W phase U phase V phase U phase V phase W phase U phase W phase U phase V phase Note: The Hall input "H" and "L" values are defined as follows: "H" means that for that phase the (+) input is higher than the (-) input, and "L" means that for that phase the (+) input is lower than the (-) input. However, note that an input potential difference corresponding to the Hall to output gain is required. Timing Charts Hall inputs Synthesized waveform Note: The Hall inputs are defined as follows: U = UIN1 - UIN2, V = VIN1 - VIN2, and W = WIN1 - WIN2. Inputs to the Hall input pins must be applied in the phase order shown in the timing chart. No. 5452-3/7 LB1955 Pin Functions Pin No. 23, 24 25, 26 27, 28 16 15 13 11 9 10 8 14 1 2 3 4 5 6 7 18 22 12, 17, 19 20, 21 Pin UIN1, UIN2 VIN1, VIN2 WIN1, WIN2 UOUT VOUT WOUT LCTR VCC VREF GND Rf VG FC LIM VC PG FG FGR SH AGC NC U phase Hall element input V phase Hall element input W phase Hall element input U phase output V phase output W phase output Pin connected to the center points of the coils that are Y-connected to the U, V, and W outputs. Power supply Reference voltage output GND Output current detection Closed loop control gain switching Speed control loop frequency characteristics correction Output current limit setting Speed control PG waveform output FG waveform output (FGR shorted to GND) PG/FG synthesized output (FGR shorted to PG) PG waveform sample-and-hold circuit capacitor connection Connection for the capacitor used by the AGC circuit, which holds the input gain at a fixed level. No connection Function Recommended Special Magnetization Waveforms B A < 7/6 x B 8/6 x D C 10/6 x D Note: Note that the intersections between the special magnetization and general waveforms and the intersections between pairs of general waveforms must be set up to be 30 apart. Hall Input Order Hall input Note: The Hall input order must be set up to be W V U. No. 5452-4/7 LB1955 VG and LIM Pin Usage Output stage LIM pin: Open VG - Rf: Shorted Gm = 0.423/Rf (A/V) (Closed loop control gain) Ilim = (VREF x 27/200 - 0.2) x 4.23/3/Rf (Current limit) VG pin: Open Gm = 1/Rf (A/V) (Closed loop control gain) Ilim = (VREF x27/200 - 0.2) x10/3/Rf (Current limit) LIM - VREF: Shorted No current limit. Note: This current limiting function is for protection against unusual and abnormal currents. If a current limit level below the rated current is set, this will, inversely, result in heat generation within the IC. When the LIM pin is open, VG is shorted to Rf, and Rf = 0.47 , this will result in a current limit level of about 1.3 to 1.4 A. If this limit falls under the rated value due to mode changes or changes in the value of the Rf resistor, set the current limit to an appropriate value by applying to the LIM pin a voltage that is divided from the VREF to ground potential by resistors of a few k. Alternatively, short the LIM pin to VREF to defeat the current limit function. PG and FG Pin Output Circuits FG (FGR shorted to ground) PG (FGR shorted to PG) No. 5452-5/7 LB1955 Block Diagram UIN1 UIN2 VIN1 VIN2 WIN1 WIN2 Hall input synthesis block (linear matrix) 3-phase differential distribution circuit FG waveform synthesis PG waveform synthesis Power transistors Internal power supply No. 5452-6/7 LB1955 Sample Application Circuit WIN2 WIN1 UIN1 UIN2 VIN2 VIN1 LB1955 0 to 5 V s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of July, 1997. Specifications and information herein are subject to change without notice. No. 5452-7/7 |
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